1. Field of the Invention
The present invention relates generally to a system and method for transferring data between two data busses having different widths. More particularly, it relates to such a system and method including a digital storage buffer designed to interface the two data busses, where information is passed to the buffer sequentially from one bus and retrieved from the buffer sequentially to the other bus. Most especially, the invention relates to such a system and method including a logic circuit to interface a first data bus to a second data bus, the second data bus having a size equal to an integral fraction of the first data bus, through a First-In-First-Out (FIFO) buffer memory.
2. Description of the Prior Art
In such systems data presented from the wider bus may contain a full word, which represents the full width of the bus, or a partial word, which means that only part of the bus has valid data associated with it. The interface must recognize the invalid data in the partial word and must not pass the invalid data to the second bus.
It is known to use a perfect data aligner to recognize and eliminate the invalid data before passing the aligned data to the FIFO memory buffer. The data aligner typically consists of a multiplexer which packs data to eliminate the invalid data fields. A temporary holding register is used to store data during the packing process. Any part of a word not written to the FIFO buffer memory immediately has to be stored in the temporary holding register, and any subsequent word has to be aligned with these stored data. The resulting logic requires a substantial amount of control logic, which is a speed limitation for a high speed bus interface.